In the manufacture of integrated circuitry, post-fabrication programmability is desirable for applications that select one or more functions from a plurality of pre-fabricated circuit blocks. Programmability is also desirable for applications that need to select redundant circuit elements when not all of the circuitry or components prove operable upon testing. Antifuses are commonly used to provide such programmability. An antifuse is a component which upon activation or xe2x80x9cblowingxe2x80x9d creates a short between two conductors. The conductors can be structures such as silicon substrate and a polysilicon line; a polysilicon line and another polysilicon line; or two metal lines. Horizontal lines with one conductor type are created and vertical lines with the second conductor type are then created to form a grid. The intersection points of the grid are separated by an insulator between the two conductors. The insulator is designed to be burned or xe2x80x9cpoppedxe2x80x9d at a relatively high voltage. The isolation between the two lines is thick, and small windows are made by the insulators that are designed to be programmed at selected voltages. Typically, the grid forms an array that supports programmability for between 1,000 to 64,000 bits. Once burned, the antifuses irreversibly short the two conductor lines and thus are known as one-time programmable (OTP) antifuses.
After fabrication, a programmer can select a horizontal line and a vertical line and apply a relatively high voltage difference between these lines and xe2x80x9cpopxe2x80x9d the insulator located at the intersection point between the horizontal and vertical lines. Once popped, the horizontal and vertical lines are electrically shorted together. The quality of the connection depends on the flow of current through the dielectric of the shorted lines. It is important to keep this constant for all the antifuses in the array. For example, if the structure is formed from a metal line and a polysilicon line, the metal line has a lower resistance compared to polysilicon line. The location of the fuse would divide the total path resistance to a metal component and polysilicon component, thus varying the total resistance with the fuse location. More current would flow through the fuse at the grid corner with the longest metal line, and shortest polysilicon line. The capacitance of the grid lines can also affect the performance quality of the connection since a high capacitance can create signal transit time delays.
In one aspect, a latch includes an inverter; a pass transistor having a first terminal coupled to an input of the inverter and a second terminal coupled to a programming voltage; a first capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a first predetermined voltage; and a second capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a second predetermined voltage; wherein each of the first and second capacitors uses an antifuse.
Implementations of the above aspect may include one or more of the following. The first and second oxide layers can be positioned in the n-well active stripe. The oxide regions can be treated as PMOS transistor regions with high threshold voltages before the deposition of the polysilicon stripe. The oxide regions can be treated as NMOS transistors with high LDN implants and n+ dopant implant after polysilicon deposition and etching. The resistance of the polysilicon stripe or the n-well active stripe can be reduced using a salicide process. A metal strap can be coupled to one or more n-well active stripes with contacts placed at one or more predetermined locations to minimize n-well stripe resistance. Programming circuitry can be coupled to the n-well active stripe and the polysilicon stripe. A PMOS decoder can be coupled to the polysilicon stripe to deliver a negative programming voltage. A positive voltage can be applied to the n-well active stripe and a negative voltage is applied to the polysilicon stripe. The grid can include an array of n-well active stripes and an array of polysilicon stripes. The polysilicon stripe can be n+ doped. The n-well stripe can, be adjacent an STI isolation oxide region. A salicided polysilicon layer can be formed above the polysilicon stripe. A dielectric layer can be formed above the salicided polysilicon layer. At least one metal line can be formed above the dielectric layer. Additional elements can include one or more additional inverters; one or more additional pass transistors each having a first terminal coupled to an input of a corresponding inverter and a second terminal coupled to a programming voltage; one or more additional first capacitors each having a first terminal coupled to the input of the corresponding inverter and a second terminal coupled to the first predetermined voltage; and one or more additional second capacitors each having a first terminal coupled to the input of the corresponding inverter and a second terminal coupled to the second predetermined voltage.